The invention relates to a charge-coupled device having a semiconductor body with, at surface, a parallel section of parallel channels situated next to one another and a parallel-in/serial-out register coupled thereto, the parallel channels being mutually separated by limitation zones which extend between the parallel channels up to the serial register, while the serial register is provided with a system of clock electrodes constructed in a multi layer (m-layer) wiring system. The invention also relates to a camera provided with such a device.
Charge-coupled devices with parallel-serial transitions are present, for example, in image sensors in which information, which is stored in the form of charge packages in the parallel section, is transported line by line to the serial register and is sequentially read out at the output of the serial register for further processing. Such parallel-serial combinations are also often used in memories, for example, in SPS memories.
A device of the kind described in the opening paragraph is known from inter alia U.S. Pat No. 4,236,830. This reference discloses various parallel-serial transitions in which the parallel channels have a uniform width over their entire length, up to the serial register. The serial register is constructed as a multiphase register in which the width of the clock electrodes is so chosen that the pitch in the parallel section corresponds to a group of clock electrodes belonging t these phases. This renders it possible to put a row of charge packages simultaneously parallel in the serial register and subsequently to transport these charge packages further through the serial register by means of multiphase clocks. During the parallel-serial transport, the clock electrodes of the serial register which lie in the extension (seen at the surface) of the limitation zones between the parallel channels can be provided with a blocking voltage level while the other clock electrodes are set at an active level, so that charge can be stored below these latter electrodes.
In image sensors which are now know, the serial register includes two or three-sub-registers next to one another with lateral connections between the sub-registers. During the parallel-serial transport the charge packages of one row in the parallel section are distributed over the sub-registers via the lateral connections and then transported to a readout member through the sub-registers. This subdivision of the serial register has become attractive as a result of the ever-decreasing pitch of the parallel section which renders a high horizontal resolution possible in the recording section of the sensor, but which is no longer compatible with the pitch of the electrodes in the serial register. The use of such a composite serial register, however, is also accompanied by drawbacks. Thus it was found inter alia that the distribution of the charge over two or three-sub-registers within fixed, short time intervals is highly critical and often not optimum, and can to a comparatively high degree contribute to the so-called F.P.N. (Fixed Pattern Noise). This is intensified by the fact that the sub-registers are usually provided with separate output amplifiers which will not be entirely identical. Moreover, the parallel-serial transport requires a fairly intricate clock diagram.